A data processing system is "pipelined" if it includes a number of stages for program execution. For example, a four stage pipeline may include a fetch stage, decode stage, execution stage, and a write-back stage. During the fetch stage, a next instruction is retrieved from a memory location. Then the instruction is decoded, executed, and written back to a location in memory, or to a register. Each of these stages may require one or more clock cycles to complete. Also, simultaneously with the first instruction being decoded, a second instruction may be fetched, and while the first instruction is being executed, the second instruction may be decoded, and so forth, so that the "pipeline" remains full.
Pipelined data processing systems may incur execution penalties when a program being executed includes a change of flow instruction. When a change of flow occurs, it may be necessary for the data processing system to stop execution of program flow in order to refill the instruction pipeline.
Various schemes such as branch prediction, prefetching and conditional execution are among the techniques used to improve performance when a change of flow is incurred. However, many of these schemes add increased complexity to the data processing system and may not be effective in every environment. Therefore, a need exists for providing control over branch prediction destination prefetching and conditional execution that is adaptable for different environments.